Senior computer development engineer with 33 years experience of Digital Signal Processor (DSP) development, Device Driver development, Infrared Sensor digital signal processing and sensor analysis, and embedded development. Have both SW (primary C/C++) and HW development experience for the full development cycle of definition, document, design, development, debug, and test. Combining HW, SW and analytical experience, provides superior computer engineering capabilities over any of these skills by themselves. Flexible, self directed, and an independent thinker, capable of doing very complex work with little or no supervision.
Created highly optimal C code for projects that demonstrated Intel IA processor performance for use in doing high speed real-time Telco NFV (Network Function Virtualization) communication’s packet processing. Optimized 2 versions of a vSwitch (Virtual Switch) OVDK to get 10 Gb Ethernet packet processing rate to 23.5 MPPS (Million Packets Per Second) for the 10 GbE Niantic interfaces (23.5 MPPS was Niantic’s maximum packet rate), with bigger packets achieving full 10 GbE rates. Achieved 23.5 MPPS switching rate per port, with up to 8 Niantic 10 GbE interfaces and also full interface I/O rate of Ethernet traffic into and out of 10 VMs (Virtual Machines) and/or host tasks running real-time DPDK packet processing tasks using shared memory communication. Most endpoint VM testing was done with simple forwarding loops, but created a task for more realistic loading which separated packets into flows and logged the flow data, had a TCP/IP server for control and log data communication, which was used for multiple VM testing, with > 15 MPPS single real-time core processing, full 10 GbE rate with 2 real-time cores using the shared memory interface through the vSwitch. Moved to Haswell system with Fortville 10 Gb Ethernet interfaces, and testing with flow log program each owning 2 10 GbE interfaces. Using Haswell system with 24, 10 Gb Fortville Ethernet ports, the flow logger program, did I/O performance characterization, NFV scaling, and high speed zero loss (RFC 2544, 60 sec tests) packet processing rate tests with >180 MPPS 64 byte, bidirectional, >360 MPPS I/O rate), and > 380 GBit/S (bidirectional) >= 256 byte packets, on a single 2 socket, 14 core per CPU, IA server. Created a window’s TCP/IP client program could connect to the real-time logging program to display current data rates through program as well as for all the current flows, without affecting the real-time program’s throughput (by design). In one test case, had 6 display programs running simultaneously connected to 6 separate real-time packet programs showing current flow data rates on my laptop. Utilized traditional signal processing techniques to produce very stable, high throughput, low latency, optimized packet processing code. Created some patches for OVS with DPDK switch, including how to do shared memory communications, but groups seemed strongly focused on the lower performance traditional data center communication. Did some code optimization experiments on the already highly optimized i40e (Fortville) DPDK device driver and made about a 15% throughput improvement.
Provide ongoing support to Goodrich Inc. (UTC) for the infrared sensor cameras and related support software used in the U2 reconnaissance platform.
The primary focus of the work was to characterize, evaluate strengths and weaknesses, optimize, and create recipe and network performance data for Intel architecture based Linux KVM COTS servers used as VM servers targeted for cloud and communications/telco type reference systems. Linux network performance was characterized for Linux KVM for VM to Host, VM to 10 GbE Interface (Intel Niantic), and VM to VM interfaces for virtio and vhost interfaces using single and multiple VMs. Network communication performance studies included PCI Pass-through and SR-IOV operation, Linux KVM compared to VMware ESXi 5.0, Linux Bridge compared to Open vSwitch (OVS) bridge SDN under OpenFlow control using Floodlight, low power blade server (low CPU clock speed) vs. rack servers, performance scaling as VMs are added, DPDK on host and DPDK in VM, using Cave Creek/Granite Hill crypto accelerators, and Huge Page vs. standard page operation. A set of affinitization optimization rules was created for network performance optimization that could be applied to multiple VMs on a system rather than to affinitization optimization of a single VM.
Modified Linux-2.6.36 and Linux-126.96.36.199 kernels and also Intel’s IXGBE 10 Gigabit Ethernet SMP Device Driver to do IP network stack processing performance measurements to research characteristics of potential network stack improvement algorithms. Implemented IP network socket to device driver polling for UDP and TCP data de-queue and also Select and Poll socket operation modifications for the receive IP protocol stack, which calls from the IP socket management code to the device driver to flush received Ethernet packets through the IP stack that are in the Ethernet receive queue for the particular SMP CPU core, but still waiting to be processed by an interrupt. Other algorithms include interrupt rate change and IP packet flow routing matched to SMP core which allowed different SMP cores for transmit and receive processing. Studied and did detailed IP stack processing algorithm CPU usage measurements from socket to interrupt processing for both transmit and receive for the linux-188.8.131.52 kernel. Measured and evaluated network communication performance of newer 8 core CPU, under development, for performance comparison with the current Nehalem and Westmere 4-6 core production CPUs.
Infrared Electrical Optical Engineer: Did testing, analysis and optimization of high throughput, high performance, cryogenically cooled, airborne infrared “Military Asset” camera used in the “U-2 Dragon Lady”. Analyzed sensor data, test results and improved the in field performance of best of its type, infrared sensor system by careful testing, data evaluation, and writing better tuning algorithms. Created and modified C/C++ applications and algorithms using Microsoft Visual Studio for the test of infrared sensor FPA (Focal Plane Array) chips (carefully wrote 108863 lines of C/C++ code for this test program), test of infrared sensor cameras, logging operation data from cryogenic focal plane cooler and for the display and evaluation of infrared sensor data. Did many sensor system data and performance studies including InSb detector flasher, oscillation, readout circuit voltage bias optimizations, FPA vacuum bakes analysis, sensor chip vacuum bakes and summarized in documents.
Night Vision Power Supply Testing Programs: Provided some support as needed to improve and correct the test of night vision goggle and scope power supplies using C/C++ test programs. Improved power supply tests on production line and to lowered testing times to improve production factory test throughput. However, primary work was with the cryogenic cooled infrared sensor systems.
MP3 Player: ADSP-BF531 Blackfin DSP, SRAM, NOR FLASH, 16MByte SDRAM (Test only), SPI EEPROM, 32 MByte NAND FLASH, Smart Media Card (for NAND FLASH firmware development), and SD Card Interface. ISP1362 OTG USB, TEA5767 FM Radio, Serial Audio A/D and D/A with Microphone and FM input, LCD with 5V boost regulator, Li-Ion Battery with charger, CPU internal voltage regulator with CPU settable 3.3V, 3.0V, 2.89V, and 2.6V system voltages, created ORCAD schematics and did hardware debug and test.
Video and Audio Media Station: Video and Media station with support MP3 player. Did architecture evaluation for embedded DSP and AU1500 design, low feature specialized MPEG2 DVR processor design, and P4 based design. P4 design provided the lowest cost and able to meet peripheral and feature requirements. Orcad schematics for PCI1620PDV FLASH media subsystem, CH7009B DVO to DVI, S-Video, composite interface, and AC97 AD1985 audio with 6 chan input and 6 channel output and digital SPDIF interface. Studied multiple Intel provided P4 reference designs and P4 mother board layout documents.
FLASH Media SW development card: For Compact Flash, SD Card, Smart Media Card, Memory Stick, and Multi-Media Card. PCI test card based on TI PCI1620PDV interface chip. Created Orcad schematics and did Orcad board layout.
Low Cost Cigarette Lighter Power Supply: 12V to 5 V,1 amp (up to 2 amp with change or resister and inductor) buck regulator based. Created Orcad schematic & board layout.
MCF5280 ColdFire Controller Board: Architecture Documents and Orcad schematics. 8 Meg SDRAM, Ethernet, RTC, 16 channel 10 bit A/D, numerous connectors and CPLD for digital I/O.
ProShare Video Conferencing: Developed and optimized ISDN communications board C/C++ embedded software. Device Driver development included Sound, ISDN B Channels, and Audio Interface for SPOX RTOS operating system. DSP MIPs Optimization, Memory Measurement and Memory Optimization, Sound Mixer modifications, H320 Video Optimization, G728 Audio Compression and Decompression, Audio Format converters, Firmware Loader, DSP runtime task load measurement and display. PC applications created: using C/C++ included Window’s runtime system memory block use classifier (for all programs in memory), ProShare application runtime memory use analysis, presented results to team, and wrote a paper for the group on Window’s memory use optimization. Window’s GUIs, VXDs, DLLs and Applications and edited embedded code created using Microsoft Visual Studio.
PBX Communications Board: DSP running SPOX RTOS operating system, similar to ProShare ISDN board, but with a PBX 2B+D interface. Project Lead for embedded DSP C/C++ firmware/software development. Did scheduling, task management, coordinated with program manager, HW team, and PBX manufacture. Created PBX D channel device drivers, call management applications, and call stack code using Microsoft Visual Studio and conforming to TAPI (Telephone API) library. Telephone B Channel Device Drivers included 8 KHz digital stream, HDLC, V120, V110, and PBX proprietary formats. Did hardware debugging and test for portions of the hardware and recommended hardware design modifications to allow for robust software and operation improvements. Created a digital modem program and communications stack and then demonstrated operation using C/C++ application created with Microsoft Visual Studio. Followed telecommunications requirements and helped with certification tests at CCL (Communications Certifications Laboratory) and passed all certification tests. Attended SPOX training class.
Embedded NetBSD Device Driver Development: Developed embedded 32 bit ARM RISC uPC code on embedded NetBSD platform to manage Infiniband data switch interface bus. Device Drivers written in C/C++, compiled with gcc, include: Operating System Real-Time Clock, CMOS Battery Backed Memory, System Timer and Dead-man Reset Timer which were 8 bit devices on 32 bit non-byte decoded bus. Also created interface card slot management device drivers for hot insert, removal, power management, status change interrupts, for each Infiniband interface card (9 interface card slots in switch), and interface card type detection and configuration. Utility baseboard drivers include fan control and monitor and I2C for multiple system temperature sensors. Created BSD 4.4 UNIX type (evolved into NetBSD) Kernel and Device Driver Auto-Configuration code to configure and attach a new bus, new multifunction devices, and add the device drivers. Created additional Embedded LINUX Device Driver set from the BSD device drivers by changing OS driver support calls since the LINUX base driver models are based on the BSD driver model. The embedded development platform’s drive was mounted on LINUX test system, which was made available to PC as a mapped drive though SAMBA allowing Microsoft Visual Studio to directly access the code files on the test system. Control and compilation was through a network terminal connection to the test system. CVS was used as source control.
LINUX based PC BIOS Test System: Created LINUX based BIOS test platform of the BIOS, Real Mode BIOS functions and Protected Mode BIOS functions without being restricted to DOS as a test system. LINUX Kernel modifications included reserving lower 1 MB memory, terminating LINUX and jumping into Real Mode 16 bit executable code, and memory mapping modifications to allow the BIOS and BIOS Flash PROM to be mapped into and accessed by user test programs. Used Microsoft Visual Studio as editor to create C/C++ LINUX programs/applications included a 16 bit executable program loader, a LILO boot memory usage analyzer, real mode test program execution environment, and test result data collection. LINUX user mode C/C++ system service libraries written included LDT (Local Descriptor Table) management (LINUX has only GDT (Global Descriptor Table) support), BIOS and Flash memory mapping, 16 bit protected mode calling interfaces with before and after call register logging features for making BIOS calls, and user mode calling support for BIOS calls for DMI, SMBIOS, BIS, PnP, and CMOS management. DOS compiled 16 Bit Real Mode libraries to build test programs included a ctr0.asm program entry code replacement which removed the requirement of DOS execution environment, some simulated DOS operating system call subroutines, and an environment specific memory manager which allowed most of the Microsoft 16 bit runtime libraries functions to be linked. Created some “Operating System Not Present”, 16 bit real mode executable test programs, for LINUX test environment. Other work outside the LINUX included creating several BIOS tests for Intel’s BEL (BIOS) Test Group and also did some BIOS boot security work. CVS was used as source control.
Casino Gaming Data Network System Programmer: Embedded software Project Lead for network gaming control and data node. Ported PSOS+ RTOS to a new highly integrated National protected mode x86 code compatible uPC with many support interfaces on one chip. Created a PSOS+ board support package, including the uPC memory and device enable and configuration, and did all of the Device Driver development for the network node. Created the serial port driver and used for PSOS+ debugger through serial port and later used the Ethernet Driver for the debugger interface. Device Drivers I created include: driver for multiple 16550 type UARTs serial ports, 10 Mbit Ethernet SMC91C94, 16 bit AD1812 Sound Chip, Intel I82365SL and Cirrus Logic PD6722 PCMCIA Slot Access Interfaces, 22 Interrupt 8259 based PIC (Programmable Interrupt Controller) manager and interrupt entry code, ISA PnP Enabler, Device Driver for 6 Channel DMA Controller, PSOS+ specific Serial Console Driver, SFF-8020i and Errata C ATAPI CD-ROM Device Drivers, and GPIO (General Purpose I/O) pin manager. Created, debugged, and tested an ISO 9660 CD-ROM File System and Casino Sound Play TCP/IP server application for MS Wave files from CD-ROM into audio system. Created, debugged, and tested PC based PCMCIA Bootload system, which included PC BIOS Boot EPROM which used an Intel I82365SL PCMCIA Slot Controller, PSOS+ Operating System Loader, PSOS+ TCP/IP (BSD type) Server, and a Windows Socket TCP/IP Client application. Brought up new hardware, did hardware debugging, and also created some prototype hardware to assist in hardware testing during project. Used an Ethernet and TCP/IP Network Analyzer and also used network monitoring programs to verify correct operation of the network driver and TCP/IP communications stack. All code was C/C++ with windows applications written and tested with Microsoft Visual Studio and Microsoft Visual Studio used as the primary editor for the embedded code.
Casino Gaming Card Reader and Display: Did device driver development and created, debugged, and tested C/C++ embedded code for a new Casino Card Reader and Display product as a replacement and upgrade to an older product. Programmed to server protocol requirements, did communications protocol coding and decoding, and data display formatting.
Embedded Firmware for Dual Modem: Developed embedded C/C++ modem firmware on embedded National CR32 CPU development platform. Created modem firmware for the computer to modem communications interfaces, the AT parser and command processor compliant to a large number of specifications, and the data communications management, flow control, in stream AT commands all programming between computer interface to the huffman compression and decompression modem interface. I created modem control code for compliance to PnP 1.0a, PnP COM, DTE V.24, USART, UART, V.25ter and Annex A, MS Unimodem, #UD and MDK, V.80, V.voice, V.8, V.8bis, FAX EIA/TIA-578 and T.31, Caller ID, V.pcm, V.34, V32bis, V32, V22bis, V22, V21, Bell 212, Bell 103 specifications. Device driver development includes computer communications interface, runtime driver management, Autobauder, Critical Interrupt Management, and PnP code. Used Microsoft Visual Studio as editor and quick test compiles for code syntax checks some code debugging in a limited code test harness application. Used National CR32 CPU and GNU based (gcc) cross compilers and tools, for building modem firmware. Used MKS Source Integrity for source code control.
Modem Hardware Development and Test: Hardware simulation of the DMA based serial port interface was done before turning a SOC ASIC by using a large FPGA connected to a embedded development platform. Since the FPGA was slow and the control clock slower compared to normal ASIC hardware, I designed a PAL based clock synchronization circuit to reliably connect test interface to the embedded development platform. I tested by using C/C++ Microsoft Visual Studio application and did hardware debugging using logic analyzer, finding multiple hardware bugs for the ASIC designer to correct before ASIC was created. Corrected by reloading new FPGA programming and retested hardware.
Ultrasound Data Collection: Did hardware design for data collection board to collect data and transfer to process with a Macintosh computer. Project Lead Engineer for 32 MHz Pipelined Data Board for Ultrasound Signal Processor. Developed Architecture Design & Doc. Design included ABT, DRAMs, Sync FIFOs, & Surface Mount.
Year 2000 Update: Did year 2000 BIOS C code updates for12 BIOSes for 15 embedded x86 based Industrial Computer Boards. Used PVCS and also MKS Source Integrity source code control, Microsoft MASM Assembler, and the Microsoft C compiler to change the Award and the Phoenix type BIOS code.
New BIOS and BIOS ROM: Created a C code and assembly Phoenix type BIOS EPROM, modified and tested it for an industrial computer board. During this contract, I also experimented with a low cost alternative BIOS, created a BIOS requirement specification, and created a BIOS test plan for a new industrial board that was being developed.
Telephone Switch Clock System: Used editor of Microsoft Visual Studio to write embedded C/C++ firmware for central office telephone switch. Compiled, debugged, and tested using VxWorks RTOS, Tornado Debugger, and PowerPC uPC ICE for telephone clock selection, synchronization and distribution to telephone switch chassis. Created T1 and E1 device drivers, line statistics, did control signal (AIS, LOS, LOF, RAI) integration and control tasks for embedded PowerPC uPC. CVS was used as source control.
Modem Data Pump Code: Created, tested, profiled and debugged DSP Modem Pump code. Simulated, developed algorithms, and plotted results using Matlab. Validated processing sequence using Floating Point and Integer Simulations on PC using Microsoft C program. Resultant C code was ported to TMS320C51 DSP, reviewed the compiled assembly generated by compiler, then created hand optimized assembly code (quicker method then going strait to hand assembly) using the C code as comments.
Warehouse Management System: Network consultant for the development of a warehouse merchandise warehouse management system. Advised and Educated on UNIX TCP/IP Socket communications. Created window’s C/C++ application using Microsoft Visual Studio which included Asynchronous WSA TCP/IP data flow monitoring, logging, and runtime data display. Application was used to assist in integration of product management computer to the real-time factory control computers. Recommend and resulted in TCP/IP protocol changes to systems being integrated to provide a reliable and robust communications protocol.
Scanning Infrared Sensor Signal Processor (SIRSSP): Project manager, architect, and primary design engineer for pipelined Digital Signal Processor (DSP) with an input data rate of 27 million samples per second with numerous algorithms processed at 16 bits. Sensor data sequence and some algorithm variations was controlled by micro-programmed sequencers with microcode compiled on VAX, using compiler that I created, and loaded by 68000 embedded processor via VAX DR11W. SIRRSP consisted of 7 large boards with approximately 200 integrated circuits each. The most complex algorithm executed was a 2-D filter with a computation rate of 3.5 billion multiples and adds per second. Embedded 68000 uPC firmware and device drivers that I wrote was approximately 5000 lines C code and 3000 lines assembly. I did the hardware design, purchased parts, sent out 75% of the boards for proto wiring (30 gauge coated copper wire routed and glued to board), assembled, did hardware debugging and verification of expected operation of all hardware processing sections using logic analyzer, found some minor hardware bugs and changed to ideal operation. Demonstrated SIRSSP by showing proper operation of the signal processing of infrared sensor bombarded by strong radiation, the first time it was used. Conducted extensive digital signal processing algorithm simulations prior to the designing of the Digital Signal Processor (DSP) hardware.
Infrared Sensor Digital Signal Processing R&D: Infrared Sensor Processing Research and Development included Digital Signal Processing algorithm development, noise modeling, data modeling, telescope modeling, IR sensor and image convolution models, did extensive simulations, did tradeoff studies, collected sensor data, experimented with sensor data, attended conferences and meetings, and presented data and results at meetings. Participated in writing contract proposals, attending contract meetings, and presented performance data, operation theory, simulation results and contract results. Provided support for large 747 mounted IR telescope by algorithm support for Cray simulations, some HW test support, runtime data collection from IR sensor signal processor, and evaluation of data.
2-D Convolutional Filter: Designed pipelined 2-D Digital Signal Processor (DSP) filter for removal of background and for 2-D band pass filtering for pipeline Digital Signal Processor. data rate (full convolution completed for each sample) 2 MHz at 12 bits. The 11 boards had Approximately 700 ICs with 24 MACs (Multiplier & Accumulator), VAX DRW11 data injection and collection interfaces, and a 68000 embedded uPC. Created embedded firmware and developed device drivers for 68000 which resulted in about 3500 assembly lines. I did the hardware design, ordered parts, assembled (also did the wire wrap), and did hardware debugging using logic analyzer. Created VAX collection and display program using graphical data display on a tektronics grahics terminal. Went from concept to test completion and demonstrated working filter in approximately 6 ½ months.
Infrared Sensor Digital Signal Processor: A Scanning Infrared Sensor Digital Signal Processor (DSP) prototype and Infrared Sensor Emulator was designed, built, tested and installed in the missile defense center test bed in Huntsville AL. I did hardware design for serial interface (Z80 based) from DSP to the Data Processor, designed parallel interface to the VAX DR11W, and 3 channel data interface card from 3 bit slice processor outputs, and designed in a 68000 VME card to do data correlation and communications. I used uPC emulator and logic analyzer to do hardware debugging, and to verify correct hardware operation. Created and debugged embedded 68000 uPC firmware and device drivers for across band channel data report correlation, data report formatting and data output to Data Processor and VAX computer. I wrote real-time data collection program for the VAX including a VAX Device Driver for DR11W parallel interface for collecting data from the Digital Signal Processor. This program included data logging, graphical display of sensor data, and post playback of logged data. Towards end of the project, the Sensor eEmulator and Digital Signal Processor were not reliable (not my part of the design), so I redesigned the hardware timing circuitry and rewired about 50% of the emulator and the Digital Signal Processor’s cards timing circuitry (rewired about 4 ½, 19 inch rack mounted drawers of wire wrap prototype hardware, about 12 cards per drawer, with about 80 ICs per board). On delivery, the hardware that I worked on was assemble and working in a hour, It was reliable, so I spent the most of the 2 week trip improving the VAX data display program adding graphical time log playback using data time stamps and did graphical user interface enhancements. This VAX program was used extensively by users of the infrared signal processing test bed.
Part of “IEEE 1355” balloting committee: IEEE Standard for Heterogeneous Interconnect (HIC)(Low-Cost, Low Latency Scalable Serial Interconnect for Parallel System Construction) http://ams.cern.ch/AMS/Electronics/Docs/1355-1995.pdf.
Oregon State University, BS Electrical and Computer Engineering, 1983.
Portland State University, Graduate Level classes, 2003